Generally, a PRAM has a cell array region and a peripheral circuit region in which semiconductor discrete devices are arranged. The cell array region has gate patterns on a main surface of a semiconductor substrate and phase change layer patterns above the gate patterns. The cell array region has a plug for electrically connecting a gate pattern and a phase change layer pattern in one cell. In the PRAM, a change of phase of the crystal structure of the phase change layer pattern is initiated using current flowing through the gate pattern and the plug. The phase change of the crystal structure of the phase change layer pattern can change data of the cell of the PRAM. The peripheral circuit region has other gate patterns on the main surface of the semiconductor substrate, but does not have phase change layer patterns above the other gate patterns. Also, the other gate pattern is located adjacent to the cell array region and transmits the data of the cell of the cell array region.
However, the PRAM typically does not have a gate pattern having high design pattern fidelity on the semiconductor substrate due to gradual reduction of a given design rule. This is because a photolithography process has a limit in defining a pattern image on a photoresist layer corresponding to the reduced design rule. In addition, the gate pattern in the cell array region has a poor current driving capability compared to that prior to the reduced design rule, such that there is difficulty in rapidly changing the phase of the phase change layer pattern. Accordingly, the plug between the phase change layer pattern and the gate pattern needs to be formed in a material capable of minimizing current loss.
U.S. Pat. No. 6,429,484 to Bin Yu (the '484 patent) discloses a multiple active layer structure and a method of making such a structure. According to the '484 patent, the structure and the method include a first layer having an oxide layer, a first active semiconductor layer, and a first insulating layer stacked in sequence. A second active layer is formed on the first insulating layer and is recrystallized by using a first seed window in the first insulating layer. Further, a second insulating layer is formed on the second active layer.
The structure and the forming method further include a third active layer on the second insulating layer. The third active layer is recrystallized by using a second seed window. The second seed window aligns the first seed window. At least one transistor is located on at least a portion of the first active layer. At least other transistor is formed on at least a portion of the second active layer. Further, at least still other transistor is formed on at least a portion of the third active layer.
However, in the structure and the forming method, if the thicknesses of the first and second insulating layers are too small, source or drain regions of the transistors on the first through third active layers may contact each other. As a result, the respective transistor has source and drain regions having different resistance values. Accordingly, the transistors may exhibit undesired performance characteristics.